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<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle">
<div class="title">cy_stc_gpio_prt_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__gpio.html">GPIO         (General Purpose Input Output)</a> &raquo; <a class="el" href="group__group__gpio__data__structures.html">Data Structures</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>This structure is used to initialize a port of GPIO pins. </p>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a3ad84c6941c092aeb4b7d04b0727f58c"><td class="memItemLeft" align="right" valign="top"><a id="a3ad84c6941c092aeb4b7d04b0727f58c"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__gpio__prt__config__t.html#a3ad84c6941c092aeb4b7d04b0727f58c">out</a></td></tr>
<tr class="memdesc:a3ad84c6941c092aeb4b7d04b0727f58c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initial output data for the IO pins in the port. <br /></td></tr>
<tr class="separator:a3ad84c6941c092aeb4b7d04b0727f58c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9245446d3c67ef24680e7efa14a8a123"><td class="memItemLeft" align="right" valign="top"><a id="a9245446d3c67ef24680e7efa14a8a123"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__gpio__prt__config__t.html#a9245446d3c67ef24680e7efa14a8a123">intrMask</a></td></tr>
<tr class="memdesc:a9245446d3c67ef24680e7efa14a8a123"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt enable mask for the port interrupt. <br /></td></tr>
<tr class="separator:a9245446d3c67ef24680e7efa14a8a123"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a48aff556861a97796f9e8aa9dbdc8e64"><td class="memItemLeft" align="right" valign="top"><a id="a48aff556861a97796f9e8aa9dbdc8e64"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__gpio__prt__config__t.html#a48aff556861a97796f9e8aa9dbdc8e64">intrCfg</a></td></tr>
<tr class="memdesc:a48aff556861a97796f9e8aa9dbdc8e64"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port pin interrupt edge detection configuration. <br /></td></tr>
<tr class="separator:a48aff556861a97796f9e8aa9dbdc8e64"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4a168a4cb7fbd62bb5b5c4016369e819"><td class="memItemLeft" align="right" valign="top"><a id="a4a168a4cb7fbd62bb5b5c4016369e819"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__gpio__prt__config__t.html#a4a168a4cb7fbd62bb5b5c4016369e819">cfg</a></td></tr>
<tr class="memdesc:a4a168a4cb7fbd62bb5b5c4016369e819"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port pin drive modes and input buffer enable configuration. <br /></td></tr>
<tr class="separator:a4a168a4cb7fbd62bb5b5c4016369e819"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a123b2b27c47fba1ebea339fa1e657f9d"><td class="memItemLeft" align="right" valign="top"><a id="a123b2b27c47fba1ebea339fa1e657f9d"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__gpio__prt__config__t.html#a123b2b27c47fba1ebea339fa1e657f9d">cfgIn</a></td></tr>
<tr class="memdesc:a123b2b27c47fba1ebea339fa1e657f9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port pin input buffer configuration. <br /></td></tr>
<tr class="separator:a123b2b27c47fba1ebea339fa1e657f9d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a762edbdcbfa88173e805a8577b33c52f"><td class="memItemLeft" align="right" valign="top"><a id="a762edbdcbfa88173e805a8577b33c52f"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__gpio__prt__config__t.html#a762edbdcbfa88173e805a8577b33c52f">cfgOut</a></td></tr>
<tr class="memdesc:a762edbdcbfa88173e805a8577b33c52f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port pin output buffer configuration. <br /></td></tr>
<tr class="separator:a762edbdcbfa88173e805a8577b33c52f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3d8fa53684ea40041db124e3da5412db"><td class="memItemLeft" align="right" valign="top"><a id="a3d8fa53684ea40041db124e3da5412db"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__gpio__prt__config__t.html#a3d8fa53684ea40041db124e3da5412db">cfgSIO</a></td></tr>
<tr class="memdesc:a3d8fa53684ea40041db124e3da5412db"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port SIO pins configuration. <br /></td></tr>
<tr class="separator:a3d8fa53684ea40041db124e3da5412db"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acaf2429c91f5de7f64f6b007c00ed35d"><td class="memItemLeft" align="right" valign="top"><a id="acaf2429c91f5de7f64f6b007c00ed35d"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__gpio__prt__config__t.html#acaf2429c91f5de7f64f6b007c00ed35d">sel0Active</a></td></tr>
<tr class="memdesc:acaf2429c91f5de7f64f6b007c00ed35d"><td class="mdescLeft">&#160;</td><td class="mdescRight">HSIOM selection for port pins 0,1,2,3. <br /></td></tr>
<tr class="separator:acaf2429c91f5de7f64f6b007c00ed35d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a512073c3eb872e2b7d53a5e43ee6aef5"><td class="memItemLeft" align="right" valign="top"><a id="a512073c3eb872e2b7d53a5e43ee6aef5"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__gpio__prt__config__t.html#a512073c3eb872e2b7d53a5e43ee6aef5">sel1Active</a></td></tr>
<tr class="memdesc:a512073c3eb872e2b7d53a5e43ee6aef5"><td class="mdescLeft">&#160;</td><td class="mdescRight">HSIOM selection for port pins 4,5,6,7. <br /></td></tr>
<tr class="separator:a512073c3eb872e2b7d53a5e43ee6aef5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae45a5b55868813fc798f154897a2f02c"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__gpio__prt__config__t.html#ae45a5b55868813fc798f154897a2f02c">cfgSlew</a></td></tr>
<tr class="memdesc:ae45a5b55868813fc798f154897a2f02c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Port slew rate configuration.  <a href="#ae45a5b55868813fc798f154897a2f02c">More...</a><br /></td></tr>
<tr class="separator:ae45a5b55868813fc798f154897a2f02c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8ed05a164d9c2be87d994215ca0d6b61"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__gpio__prt__config__t.html#a8ed05a164d9c2be87d994215ca0d6b61">cfgDriveSel0</a></td></tr>
<tr class="memdesc:a8ed05a164d9c2be87d994215ca0d6b61"><td class="mdescLeft">&#160;</td><td class="mdescRight">Drive strength configuration for pins 0,1,2,3.  <a href="#a8ed05a164d9c2be87d994215ca0d6b61">More...</a><br /></td></tr>
<tr class="separator:a8ed05a164d9c2be87d994215ca0d6b61"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:adc09324003007e956be2d8bc0e9e7004"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__gpio__prt__config__t.html#adc09324003007e956be2d8bc0e9e7004">cfgDriveSel1</a></td></tr>
<tr class="memdesc:adc09324003007e956be2d8bc0e9e7004"><td class="mdescLeft">&#160;</td><td class="mdescRight">Drive strength configuration for pins 4,5,6,7.  <a href="#adc09324003007e956be2d8bc0e9e7004">More...</a><br /></td></tr>
<tr class="separator:adc09324003007e956be2d8bc0e9e7004"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae4dac6192992209fc667e67335002755"><td class="memItemLeft" align="right" valign="top">uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__gpio__prt__config__t.html#ae4dac6192992209fc667e67335002755">nonSecMask</a></td></tr>
<tr class="memdesc:ae4dac6192992209fc667e67335002755"><td class="mdescLeft">&#160;</td><td class="mdescRight">HSIOM non secure mask for port pins 0-7.  <a href="#ae4dac6192992209fc667e67335002755">More...</a><br /></td></tr>
<tr class="separator:ae4dac6192992209fc667e67335002755"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Field Documentation</h2>
<a id="ae45a5b55868813fc798f154897a2f02c"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae45a5b55868813fc798f154897a2f02c">&#9670;&nbsp;</a></span>cfgSlew</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">uint32_t cy_stc_gpio_prt_config_t::cfgSlew</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Port slew rate configuration. </p>
<dl class="section note"><dt>Note</dt><dd>This parameter is available for the CAT1B and CAT1D devices. </dd></dl>

</div>
</div>
<a id="a8ed05a164d9c2be87d994215ca0d6b61"></a>
<h2 class="memtitle"><span class="permalink"><a href="#a8ed05a164d9c2be87d994215ca0d6b61">&#9670;&nbsp;</a></span>cfgDriveSel0</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">uint32_t cy_stc_gpio_prt_config_t::cfgDriveSel0</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Drive strength configuration for pins 0,1,2,3. </p>
<dl class="section note"><dt>Note</dt><dd>This parameter is available for the CAT1B and CAT1D devices. </dd></dl>

</div>
</div>
<a id="adc09324003007e956be2d8bc0e9e7004"></a>
<h2 class="memtitle"><span class="permalink"><a href="#adc09324003007e956be2d8bc0e9e7004">&#9670;&nbsp;</a></span>cfgDriveSel1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">uint32_t cy_stc_gpio_prt_config_t::cfgDriveSel1</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Drive strength configuration for pins 4,5,6,7. </p>
<dl class="section note"><dt>Note</dt><dd>This parameter is available for the CAT1B and CAT1D devices. </dd></dl>

</div>
</div>
<a id="ae4dac6192992209fc667e67335002755"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ae4dac6192992209fc667e67335002755">&#9670;&nbsp;</a></span>nonSecMask</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">uint32_t cy_stc_gpio_prt_config_t::nonSecMask</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>HSIOM non secure mask for port pins 0-7. </p>
<dl class="section note"><dt>Note</dt><dd>This parameter is available for the CAT1B and CAT1D devices. </dd></dl>

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